Does an ATX PLL configured as a Clock Buffer need a reference clock of it's own or can the pll_refclk0 port be tied to ground?

HI,

I am not familiar with Interlaken GEN 2 design implementation but below is the ground rule of refclk connection of the ATX_PLL that act as clock buffer

1. If planning to reconfigure this clock buffer ATXPLL into a Main ATXPLL please connect pll_ref_clk0 to the appropriate refclk source
2. Otherwise, it's safe to tie it off like to GND as the design block doesn't function as PLL, it's merely function as clock buffer only

I believe the reference design operate using option 2. That's why you see clock buffer ATX_PLL refclk pin is tied to GND.

Thanks.

Regards,

dlim