Documentation for Cyclone 10 GX core components?

​Thank you!

Unfortunately, that document doesn't provide me with additional information regarding the cyclone10gx_ddio_in module being instantiated within the altera_gpio_one_bit module. The GPIO when instantiated, interfaces with an altera PHY transceiver instance on the following logical port pins:

pipe_phy_status

pipe_rx_status

pipe_rx_valid

rx_data

rx_datak

Here is a code snipped showing the actual connections:

wire [23:0] pipe_rx_phy = {1'b0,

pipe_phy_status, // 1 bit

pipe_rx_status, // 3 bits

pipe_rx_valid, // 1 bit

rx_datak, // 2 bits

rx_data // 16 bits

} /* synthesis keep */;

wire [23:0] pipe_rx_h;

wire [23:0] pipe_rx_l;

// Instantiate GPIO in DDIO register mode

mf_ddio_rx ddio_rx (

.datain (pipe_rx_phy),

.clk (local_clk),

.dataout_h (pipe_rx_h),

.dataout_l (pipe_rx_l)

);

where can I find additional information about the cyclone10gx_ddio_in module?

Regards,

Luis