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Altera_Forum's avatar
Altera_Forum
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11 years ago

Do I need pcie_reconfig_driver, pcie hardcore

I’m doing my first pcie design with altera. I’m using the qsys flow implementing a gen1 x1 pcie with Avalon-mm interface. I have to say I’m really having a difficult time understanding how to get it all bolted together. There are lots of documents and some videos, but it’s my opinion that they spend more time describing the water than teaching me how to swim.

Question:

It’s not clear to me when I must use the pcie_reconfig_driver in my design.

According to the wiki a gen1 pcie does not need the reconfig driver. In the Altera install directory there is a qsys pcie sample ep_g1x1.qsys, but it has the reconfig driver and it’s gen1. The qsys file for the Cyclone V GT FPGA Development Kit is a gen2x4, and the qsys file for the design does not have reconfig driver. If I understand correctly, I must include the alt_xcvr_recofig with any pcie implementation. When do I need the reconfig driver? What are the implications of just using it? I hate to include stuff that is not necessary to my design.

thanks

References:

Wiki: (http://www.alterawiki.com/wiki/configuring_the_transceiver_reconfiguration_controller_and_the_pcie_reconfig_driver_for_stratix_v_and_arria_v_gz_pcie_hard_ip_designs)

Location of ep_g1x1.qsys: c:\altera\14.0\ip\altera\altera_pcie\altera_pcie_cv_hip_avmm\example_designs

Cyclone V kit link:

http://www.altera.com/products/devkits/altera/kit-cyclone-v-gt.html

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    The pcie_reconfig_driver is required if the PCIe core is generated as Avalon-ST interface.

    The pcie_reconfig_driver is not required if the PCIe core is generated as Avalon-MM interface.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    The pcie_reconfig_driver is required if the PCIe core is generated as Avalon-ST interface.

    The pcie_reconfig_driver is not required if the PCIe core is generated as Avalon-MM interface.

    --- Quote End ---

    Is this also the case for PCIe 3.0 x8?