Hi...i am tring to copy memory from sram to sdram using dma. For some reason some of the data dosent transfered... Are there any suggestions what to look for to solve this problem? Thanks. Asaf

Might be caused by the cpu reading data from the data cache, and/or writing dirty cache lines back over the copied data.

does the sgdma has the same functions

how can I fix the dirty cache lines?

I'm assuming you are trying to do something like this: 1) Using Nios II to populate some buffer in memory (lets call this buffer A) 2) DMA data from buffer A to another buffer (lets call this buffer B ) 3) Using Nios II to read back buffer B Doing this the data written in# 1 should be the same as the data read back in# 3 but due to the cache this isn't happen. So for# 1 to be safe you need to ensure the data is not cached and reaches the memory. There are two ways you can do this, A) if you are using pointers remap the pointer to be a cache bypassing pointer, or B ) after you write to the buffer perform a cache flush (just flush the range of address where your buffer resides in memory). When this is done then you can start the DMA. For# 3 to be safe (just in case you have previously read from the buffer B locations previously) you can do something similar. Either flush those locations before the DMA transfer, or use a cache bypassing pointer to access the data after the DMA transfer. Depending on your memory latencies and buffer sizes one method will be better than the other. For example if the buffers were on-chip memory using cache bypassing pointers is probably the way to go. If it was SDRAM then flushing ranges of the data cache would probably be better due to the high latency.

dma instability | Altera Community

13 Replies

Altera_Forum
Honored Contributor
14 years ago
but i used malloc...the problem is with the dma address changing..I can see it with signal tap.
Altera_Forum
Honored Contributor
14 years ago
I'm not sure if I follow. If you mean that you think cache isn't a problem because you see the DMA addressing incrementing then that's not what we are talking about. We are talking about the data that you are accessing before and after the transfer. If you do not take care of cache coherency of the data then the DMA may not transfer the data you populated in the memory (because it may still be allocated in the cache).
Altera_Forum
Honored Contributor
14 years ago
so how do i take care of it?
i tried dcache_malloc, flush the cache before I call DMA...what else can i do?

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dma instability

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