DMA Controller is not stopping!!!

I have the sample working while back there... 2 years ago. DMA and SGDMA simple C program to execute the DMA or SGDMA....

Best,

Sean

--- Quote Start ---

Hi guys,

I had some weired behaviour of this controllers last week and I found out that it was caused by the setting of the allowed transactions. After this the DMA worked perfect (the code snipped below worked perfekt).

Today I got this behaviour again, after enabling the burst transfer, to increas the throughput.

The DMA should copy a array of data from one position of the external RAM to another one. The SDRAM Controller has also burst transfer enabled.

The DMA Parameters:

- Transfer size: 26

- Burst transfer: enable

- Maximum burst size(words): 32

- Data transfer FIFO depth: 128

- FIFO made of embedded memory blocks

- Allowed transactions: byte, halfword, word, doubleWord, quadWord;

The weired behaviour:

the whole address span will be overwritten by the dma controller, as it is not stopping copying data. (i have noticed this behaviour with the memory viewer in the nios ii debug window by pausing the debugger)

My code to configure the DMA:

// Solution ID: spr240514 - When bursting is enabled, the DMA controller must be programmed to perform transactions at its full data width.

// config: word transfer; transfer enable; transfer ends when length = 0!;

unsigned int const mask = ALTERA_AVALON_DMA_CONTROL_WORD_MSK | ALTERA_AVALON_DMA_CONTROL_GO_MSK | ALTERA_AVALON_DMA_CONTROL_LEEN_MSK;

unsigned int counter = 0;

if(length != 0)

{

IOWR_ALTERA_AVALON_DMA_CONTROL(DDR3_DMA_BASE, 0);

IOWR_ALTERA_AVALON_DMA_STATUS(DDR3_DMA_BASE, 0);

IOWR_ALTERA_AVALON_DMA_LENGTH(DDR3_DMA_BASE, 0);

//dma

IOWR_ALTERA_AVALON_DMA_RADDRESS(DDR3_DMA_BASE, DMA_RD_Addr & 0x7FFFFFFF);

IOWR_ALTERA_AVALON_DMA_WADDRESS(DDR3_DMA_BASE, DMA_WR_Addr & 0x7FFFFFFF);

IOWR_ALTERA_AVALON_DMA_LENGTH(DDR3_DMA_BASE, length);

IOWR_ALTERA_AVALON_DMA_CONTROL(DDR3_DMA_BASE, mask);

while((IORD_ALTERA_AVALON_DMA_STATUS(DDR3_DMA_BASE) & ALTERA_AVALON_DMA_STATUS_DONE_MSK) != ALTERA_AVALON_DMA_STATUS_DONE_MSK){

;

}

return 1;

}

i have found a bug report in the knowlegde base:

title

DMA Controller Always Busy in Burst Mode

description

The DMA controller component (altera_avalon_dma), when enabled for burst transactions, does not perform transfers at widths other than its full data width. The DMA controller is always busy.

workaround / fix

When bursting is enabled, the DMA controller must be programmed to perform transactions at its full data width.

the workaround is not clearly defined! I can not understand how to solve the problem in my case.

This bug is still existing in v13.1 SP1 and was found in v10.0. come on!!!

When the "Go" bit in the control register is enabled, the DMA is not stopping to copy data. It is overwritting the whole adress span --> imagin how

How embarressing, because I mean it is just an simple DMA IP-Core with a damn bug, which cause me getting a red head.

Q: Can anybody tell me what this workaround mean?

Kind regards,

Roland

--- Quote End ---