Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHello Pillemann (sounds german to me),
I do not check how the transfer ends. I set up the dma controller to end when the length register reaches zero and the driver checks that length is a integer multiple of the transfer type's length in bytes (ie. 4 or 8 in my case). I watched the length register in signal tap. It always reaches zero even if no interrupt is generated. I fixed the problem in not changing the transfer type. Every transfer is double word. That doubled the throughput, too. I normally do not reset the go bit but I tried to - without success. Only a reset before changing the transfer type soluted the problem. But the reset operation reduced the throughput significantly. My driver generates a timeout if no interrupt occures. I will check the status register after a timeout and post it. I'm using Quartus 10.0 SP1. Regards from Hamburg, Frederik