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Altera_Forum
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16 years ago

DMA and PCIe

Hi, I have SOPC system with PCIe, DDR2 and DMA. BAR0 is connected to CRA of PCIe at base 0x1000_0000. BAR1 is connected to DMA control port slave at offset 0x100. DMA's read-master is linked t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi,

Thanks for the reply. I finally got it to work when I changed my offsets to

64-bits instead of regular 32-bit. So I incremented the control reg offsets by 8, instead of 4. I have a heterogeneous system, with 64-bit data width for DDR2 and 32-bit for the PCIe. Altera's DMA manual talks about different data widths, although it doesn't directly mention how it (different data widths) affects the control registers' offsets.

I can now prime the read/write addresses, length and initiate a transfer. I can see the DDR2 being read (SignalTap-II) and the status returned as 0x11 - meaning 'done' and 'length is zero'.

However, my now PCIe destination doesn't seem to be getting the data. I think my avalon-to-PCIe address translation may be incorrect.

regards,