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Altera_Forum
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11 years ago

DisplayPort

Hi all, Normally the VESA mentions that the DP (with 4lines) is able to send 12-ppc YCbCr 4: 2: 2 (24 dpi) corresponding to 1920x1080p @ 120Hz I would like to know what will be the DTM (Disp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi Tricky,

I Have read the user guide of DP and the specification of VESA to be able to implement this IP in my own design. I was able to run the design simulation of altera with modelsim.

After that I created my owne design (DP-Sink plus thiers PHY and XCVR). The compilation passe without any error. But when I started the simulation of this design I have many error.

1- When I take a look into the DISPLAYPORT_02_run_msim_rtl_vhdl.do file I found that many file didn't compiled (exp: altera_dp_reconfig_ctrl.v)

2- The DP_SIM folder hadn't the entire file (altera_dp_reconfig_ctrl.v, altera_dp_reset_delay, altera_dp_status_sync).

I am wondring why the quartus messed to include this file in the simulation folder.

Thanks