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WFitt's avatar
WFitt
Icon for New Contributor rankNew Contributor
6 years ago

DisplayPort Source Link Training is failing sometimes. DisplayPort IP core seems to hang up.

On our Board we are using Cyclone V GX FPGA with Intel/Altera DisplayPort IP (Version 15.1, used as source, 2 lanes , 2.7 Gbps)​, connected to a NXP DisplayPort to LVDS Bridge PTN3460IBS. This constellation is working fine in hundreds of our devices. But sometimes it happens that the link Training is failing. In the attachment there is a log file with the AUX debug traces in the failing case. It can be seen that the link training is beginning correctly. Then the IP is sending the command

[SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00

forever and the sink is answering correctly each time.

The DisplayPort IP core seems to be hanged up.

Is this bug known? How could it be fixed?

4 Replies

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    It's not easy to debug link training log without the decoder.

    • Do you also have the link training passing log file to serve as reference ?

    From your link training failure log file, it's hard to tell whether this is link training failure issue or link training stuck issue.

    • Initially, I did see from the log file 0x202h (line 32, 33) that it already passed TPS1 clock recovery phase with 11h result indicating lane0_cr_done = 1, lane1_cr_done = 1
    • After that, there is whole bunch of aux_defer command. Looks like sink is not ready to process source command request
    • Finally, source started TPS1 clock recovery training again but this time it's failing.

    It's tough to isolate whether the issue is with DP source chip, DP sink chip or the board connection design itself.

    1. May I know how many failure cases so far ?
    2. Does the link training failure is intermittent issue or permanent failure issue ?

    Some debug proposal as below.

    • For DP sink - Do you have a way to monitor the status of DP sink chip to maybe indicate link training failure is caused high bit rate error (BER) or receiver channel CDR loose lock ?
    • For DP source - Quartus v15.1 is pretty old and very hard to find out whether there is any bug in the past or not. You can try upgrade to latest Quartus version like maybe v19.1 standard edition and retest the failure units again.
    • Can you lower the video resolution to 1.62Gbps data rate to see whether it helps to improve the link training result or not ?

    Thanks.

    Regards,

    dlim

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    I have not hear back from you for 2 months. Hopefully my debug suggestion help out and you are able to make progress with your project.

    For now, I am setting this case to closure.

    Thanks.

    Regards,

    dlim

  • WFitt's avatar
    WFitt
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    Our problem is solved. The AUX lines were not terminated well. Thank you for your help!

    Regards

    Wolfram