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WFitt
New Contributor
New ContributorDisplayPort Source Link Training is failing sometimes. DisplayPort IP core seems to hang up.
On our Board we are using Cyclone V GX FPGA with Intel/Altera DisplayPort IP (Version 15.1, used as source, 2 lanes , 2.7 Gbps), connected to a NXP DisplayPort to LVDS Bridge PTN3460IBS. This conste...
WFittNew Contributor
New ContributorHi,
Our problem is solved. The AUX lines were not terminated well. Thank you for your help!
Regards
Wolfram
