DisplayPort IP Example Design - VHDL

Hi,

I also realized same behavior, let me check internally with team & get back to you.

I could observe following two things which indicates that DisplayPort IP Example Design available only in Verilog HDL.

• check the Figure 2. & Table 1. from the link below

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-dp-de-17-0.pdf

• check screenshot of Warning message during generation,

Regards,

Vikas Jathar