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DZuck1
Occasional Contributor
Occasional ContributorDisplayPort IP Example Design - VHDL
Hi, I am trying to use Quartus Prime 17.0 to generate the DisplayPort IP Example Design for VHDL simulation. I followed through the directions in the UG (https://www.intel.com/content/dam/www/progr...
Vicky1
Regular Contributor
Regular ContributorHi,
I also realized same behavior, let me check internally with team & get back to you.
I could observe following two things which indicates that DisplayPort IP Example Design available only in Verilog HDL.
- check the Figure 2. & Table 1. from the link below
- check screenshot of Warning message during generation,
Regards,
Vikas Jathar
