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Michael2021's avatar
Michael2021
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

DisplayPort at non GPU mode on Cyclone 10 GX and Quartus pro 20.1

I tried to finalize design non GPU mode. doesn't provide non GPU mode example design. I can't figure it out how to connection Transceiver Native PHY Reconfiguration interface signal ( this signal i...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Does the CLKUSR pin need to be stable clock for PreSICE function, before FPGA configuration complete ?

  • Yes. CLKUSR needs to be stable and free running clock before FPGA configuration started as this is the clock source used for FPGA power up transceiver channel calibration process.


Thanks.


Regards,

dlim


  • Michael2021's avatar
    Michael2021
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Thank you

    I didn't connect the clock at there. Is there any solution how to skip this calibration process or should be there ? I think that is different point than Arria V GX.

    Michael