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Michael2021's avatar
Michael2021
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

DisplayPort at non GPU mode on Cyclone 10 GX and Quartus pro 20.1

I tried to finalize design non GPU mode. doesn't provide non GPU mode example design. I can't figure it out how to connection Transceiver Native PHY Reconfiguration interface signal ( this signal i...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Yup, looks like your design DP link transceiver channel is stuck in reset.


Transceiver NativePHY IP reset operation is managed by another IP called "transceiver PHY reset controller" IP.

  • There is one master reset input pin to this reset controller IP.
  • You may want to slowly trace back in your design how does this master reset input pin is connected and make necessary design modification. If reset controller is held in reset then your transceiver channel will be stuck in reset as well


Thanks.


Regards,

dlim


Michael2021's avatar
Michael2021
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Thanks for recommending.

I look at the rx_phy_top.v. I think they have three reset (cpu_reset_n, cpu_reset, video_pll_locked). all three signal is good signal input from external module.

Can you recommend any other signals to solve this ?

I have experience of DP design using Arriva V GX. I knew transceiver reconfiguration module have many different signal as compare with Arria V GX. I can't guess how to work configuration mechanism in Cyclone 10 GX. Does the CPU need to initialize rx_phy_top module after reset released ?

Thank you

Michael