Display port video data input interface issue

Hi Sir,

Customers have the video data interface of DP IP issue about the Hsync & Vsync state.

Documentation describes that user can use standard Hsync and Vsync as the video data input source format

but don't provide the detail information.

Customers inquired the every interval of Hsync signals whether can have different latency .

They want to add more than 3 or 5 cycles between Hsync signals at the last video line before the next frame image .

https://www.intel.com/content/www/us/en/programmable/documentation/hco1410462777019.html

Thanks​