direct instantiation of altera_mf_components IP from VHDL

Altera is shifting away from using direct VHDL instantiation for certain IP cores, especially in its newer FPGA families like Stratix 10. Instead, the focus is moving toward using tools such as Platform Designer and TCL scripts. This change helps standardize how IP cores are integrated into projects and unlocks access to advanced features that aren’t available through the older VHDL method. It also improves simulation workflows and integrates more smoothly with Altera development tools.

To keep up with these changes, IP cores must be updated within Quartus to ensure they're compatible with the latest FPGA features. As direct VHDL support becomes increasingly limited, it's a good idea to start converting your existing design libraries to the newer, tool-based approaches. Begin with the libraries most impacted by the changes.