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pdewanga's avatar
pdewanga
Icon for New Contributor rankNew Contributor
3 years ago

Differential serial Interface in avst hip

Hi Community,

Do we have the differential input in tx and rx serial interface on Avalon streaming PCIe ?

I checked the L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV)
Intel® FPGA IP for PCI Express* User Guide it's written that each lane includes a differential pair.

But the qsys generated file does not have the differential pair.

Attaching the snap of the qsys and the user guide

How to enable the differential pair for TX and RX serial interface?

4 Replies

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Thank you for reaching out.

    Just to let you know that Intel has received your support request and I am assigned to work on it.

    Allow me some time to look into your issue. I shall come back to you with findings.


    Thank you for your patience.


    Best regards,

    Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    For Stratix 10 Differential I/O , please refer to below user guide.

    It got lot more detail compare with the one you referring right now.



    Note :

    Differential SSTL input should only be used on DQs pins as DQ pins typically uses single-ended SSTL in EMIF interfacing application

    We do support Pseudo-diff for DQ pins in EMIF but not on GPIO. If using Memory IP, then DQs and DQ pins do support pseudo diff SSTL, however, since GPIO IP doesn't have differential terminator, diff SSTL is not supported on GPIO IP.

    In Table 1 of Stratix 10 IO User Guide (page 9), Diff SSTL is supported for LVDS I/O Buffers only, example of this is EMIF. (We will see if the documentation can be modified to make it clear for our customers)

    GPIO uses different data path than Memory, So GPIO doesn't have control of termination, probably PHYLite can be used to have control of bidir pins,


    Hope this clarified.

    Regards,

    Wincent_Intel




  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    I wish to follow up with you about this case.

    Do you have any further questions on this matter ?

    ​​​​​​​Else I would like to have your permission to close this forum ticket

    Regards,

    Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    I strongly believe my previous reply answered your question.

    We do not receive any response from you to the previous answer that I provided.

    This thread will be transitioned to community support.

    If you have a new question, feel free to open a new thread to get support from Intel experts.

    Otherwise, the community users will continue to help you on this thread. Thank you

    If you feel your support experience was less than a 9 or 10,

    please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience.

    Regards,

    Wincent_Intel