Differential serial Interface in avst hip

Hi,

For Stratix 10 Differential I/O , please refer to below user guide.

It got lot more detail compare with the one you referring right now.

• Intel® Stratix® 10 General Purpose I/O User Guide
  • https://www.intel.com/programmable/technical-pdfs/683518.pdf
• Intel® Stratix® 10 High-Speed LVDS I/O User Guide
  • https://www.intel.com/programmable/technical-pdfs/683792.pdf

Note :

Differential SSTL input should only be used on DQs pins as DQ pins typically uses single-ended SSTL in EMIF interfacing application

We do support Pseudo-diff for DQ pins in EMIF but not on GPIO. If using Memory IP, then DQs and DQ pins do support pseudo diff SSTL, however, since GPIO IP doesn't have differential terminator, diff SSTL is not supported on GPIO IP.

In Table 1 of Stratix 10 IO User Guide (page 9), Diff SSTL is supported for LVDS I/O Buffers only, example of this is EMIF. (We will see if the documentation can be modified to make it clear for our customers)

GPIO uses different data path than Memory, So GPIO doesn't have control of termination, probably PHYLite can be used to have control of bidir pins,

Hope this clarified.

Regards,

Wincent_Intel