Difference between "SDRAM Controller Core" and "Tri-State SDRAM Core"

Hello,

In the "embedded peripherals ip user guide" (UG-01085, 2016.12.19) it is stated on the page 36: "the altera sdram tri-state controller has the same functionality as the sdram controller core with the addition of the tri-state feature".

Nevertheless the interfaces to sdram modules of these 2 controllers are different.

For example sdram controller core has no dqm (Data Input/Output Mask) inputs.

The sdram module on my de1 board has these inputs - dqml (x16 Lower Byte, Input/Output Mask) and dqmh (x16 Upper Byte, Input/Output Mask).

It seems that these signal aren't static, i.e. they change theirs states during data transfer.

So, my question is: should I add custom control of these signals in the top wrapper module (module that wraps Qsys module instantiation) or use sdram tri-state controller, that, according to user guide (but i didn't check yet), has these controls.

Thank in advance.

Here below - block diagram of the SDRAM module with highlighted dqml/dqmh signals.

http://www.alteraforum.com/forum/attachment.php?attachmentid=13332&stc=1