Delay in CDR recover

Hi Frank,

Thank you for your support again.

For context, we are working on implementing a passive optical network (PON)-like optical switching scheme. This approach aligns with the description in an Altera note, which reports a CDR lock time of 267.5 ns in Table 1. The same note also states that “the Stratix IV and Stratix V families of FPGAs have integrated burst-mode CDR SERDES that can support a variety of optical transceivers available in the market.” This suggests that some of the Altera-provided resources could potentially be reused or adapted to enhance our current implementation.

Given that our setup employs a highly stable reference clock, we believe it should be possible to achieve a lock time even shorter than 267.5 ns. However, we have not been able to locate a suitable example project or detailed documentation that demonstrates how the burst-mode CDR is implemented on Stratix IV devices with the integrated transceiver.

Would you be able to advise where we might find the relevant reference designs or documentation? Your assistance would be greatly appreciated.

Best regards,

Hank