Forum Discussion

arlen's avatar
arlen
Icon for New Contributor rankNew Contributor
5 years ago

deinterlace IP

deinterlace II ip ，when i select 8bit or 12bit of color sample, my program is working properly, but when i select 10bit, is abnormal. The input is the same
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Unfortunately we don't have the example design.


Intel FPGA doesn't offer v18.2. I presume you are referring to v18.1.2 ?


To rule out potential old Quartus version issue,

  • pls try to upgrade to latest Quartus version if possible.
  • Since it's working on your colleague PC, you can install v18.1 on your PC to see if it's v18.1.2 version issue but I doubt so


Another thing to check is to ensure your FPGA design is timing clean to avoid design functionality failure


Thanks.


Regards,

dlim



  • arlen's avatar
    arlen
    Icon for New Contributor rankNew Contributor
    5 years ago

    hi，

    现在发现主要问题还是avalon-mm接口，发现deinterlace ip 出来的某次读突发会导致avalon-st接口的ready拉低一直不变，st接口按照协议打包正确，mm接口也是按照官方手册的时序进行操作的，但是有一点就是我同事的mm接口没有突发长度为1的时候，但是我这边频繁出现，官方对这个IP没有任何时序上的介绍，所以也不知道问题现在在哪