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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Debugging PCIe DMA transfer example design

Hi, I would like to have your continued support on this thread. Unfortunately this ticket got closed https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfe...
Pcie
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi @Sijith,


Do you have any updates regarding my previous reply?


Based on the Capture_nodes_screenshot.png you attached, the signals you added in the SignalTap look like address signals. Can you please try removing these signals and instead adding the signals of ctrl_amm_0 or Avalon Memory Mapped Slave signals?


Attaching screenshot of ctrl_amm_0 signal:

(If you are unable to view the image, please right-click on the image and click 'Open image in new tab')


Please let me know if the error goes away after making these changes.


Thanks.

Best Regards,

VenTingT