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CSegu's avatar
CSegu
Icon for New Contributor rankNew Contributor
7 years ago

Dear Sir, I am using ALTLVDS_RX IP on a Cyclone V GX device, and noticing that for some reason the rx_locked pin of PLL is never being locked. Same problem noticed when PLL is set to shared between LVDS transmitter and receiver. DPA not active.

I am using ALTLVDS_RX IP on a Cyclone V GX device, and noticing that for some reason the rx_locked pin of PLL is never being locked. Same problem noticed is PLL is set to shared between transmitter a...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
7 years ago
Hi, There could be multiple reasons for not generating the clock may be the input will not be proper. IP configuration will be proper or board level issues.