New Contributor
Occasional Contributor1. For the BG width, you should follow vendor's datasheet. As it's BG of Micron's is 1, the IP setting should be the same as it.
2. Normally, the clock should be 266.67Mhz, not 267Mhz, you can correct it.
3. Different vendor's datasheet should be different. For the memory timing parameter in IP MEM timing tab & memory tab, you should follow Micron's and modify it accordingly. I can't find any MEM timing in attached datasheet, you can contact with Micron and get the related MEM timing parameter.
4. For board tab parameter, normally you need do SI simulation with vendor's simulation model to determine the SI/corsstal value. Pls refer to below link for more detail.
https://community.intel.com/t5/FPGA-Wiki/Board-Skew-Parameter-Tool-Guide/ta-p/735276
5. After input the correct parameter, you can compile the design, and make sure there is no timing violation warning.
