Forum Discussion

New Contributor

7 years ago

DDR3 SDRAM UniPHY larger than expected latency

The UniPHY (v16.1) DDR3 SDRAM controller in my Stratix V design a shows much larger than expected latency. The DDR3 refresh is not user controlled. Largest read latency so far observed is around 185...

NurAida_A_Intel

Frequent Contributor

7 years ago

Hi Sir,

The additive latency of 1 or 2 cycles is expected to allows the device holds the commands internally for the duration of additive latency before executing. This explained in EMIF handbook (page 596).

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi.pdf

Thanks

Regards,

NAli1

Forum Discussion

DDR3 SDRAM UniPHY larger than expected latency

Recent Discussions

Cyclone-V SCFIFO with M10K/MLAB memory - adding ECC

Agilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wanted

Agilex 7 slew rate reconfiguration

Agilex-7 AXI MCDMA for PCIe hang

Constraints not being picked for DCFIFO