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WOver1
New Contributor
New ContributorDDR3 SDRAM UniPHY larger than expected latency
The UniPHY (v16.1) DDR3 SDRAM controller in my Stratix V design a shows much larger than expected latency. The DDR3 refresh is not user controlled. Largest read latency so far observed is around 185...
NurAida_A_Intel
Frequent Contributor
Frequent ContributorHi Sir,
The additive latency of 1 or 2 cycles is expected to allows the device holds the commands internally for the duration of additive latency before executing. This explained in EMIF handbook (page 596).
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi.pdf
Thanks
Regards,
NAli1
