DDR3 SDRAM UniPHY larger than expected latency

Hi Sir,

As i understand it, you are having problem with the read latency value which is much higher than expected on your controller. The latency is depend on how the traffic pattern and the controller operates.

However, seems like the current observed latency is too high as compared to the expected latency. So, I suggest you to generate the example design first and then, compare the parameter of your design and the golden design. You can refer to this handbook page 986 under chapter Uni-PHY Based Example Design.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi.pdf

For your reference, this is another design example for "Stratix V DDR3 SDRAM UniPHY 666MHz Quarter Rate". The wiki version is older and I recommended you to use the newer version.

https://fpgawiki.intel.com/wiki/Design_Example_:_Stratix_V_DDR3_SDRAM_UniPHY_666MHz_Quarter_Rate

Anyway, there is several technique and setting that can help to improve efficiency and latency of the IP. You can refer to page 593 under chapter “Ways to Improve Efficiency” in this shared link.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi.pdf

Hope this helps.

Thanks.

Regards,

NAli1