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Honored ContributorDDR3 SDRAM UNIPHY HPC problem with read
Quartusii version 13.1,CycloneV,MT41K256M16HA
The main parameters uniphy hard ipcore side: memory clock 300Mhz total interface width 32: DDR3 total bit width used is 16bits capacity of 512MB, 1GB to extend it to 32bits full rates, burst size: 128, DQ width: 64bit Avalon-MM side: data width 64, clock: 125Mhz Details: When read, the first read command is issued in response to the read DDR3 ipcore corresponding address data; cross-write operation (normal); reading instruction and reading the second instruction after the issue, did not respond ipcore (cs_n, ras_n, cas_n , we_n, mem_ba, mem_a no change), FIG. http://www.alteraforum.com/forum/imagehttp://www.alteraforum.com/forum/attachment.php?attachmentid=12619&stc=1 Best ragards LSR2 Replies
Altera_ForumHi,everyone
I have found why the read signal is normal，but can not reproduce the DDR data . Avalon-MM protocol: In busrt Write operation,the local_ready signal is low and indicate the slave not ready to receive write commands from the master,so write command remains unchanged until local signal high and this burst write operation is complete.ortherwise,it will lead to the subsequent read signal is not be ipcore response. ----------Poor english,if wrong please advise,thank you------------ LSR- Altera_Forum
Hi,everyone
I have found why the read signal is normal，but can not reproduce the DDR data . Avalon-MM protocol: In busrt Write operation,the local_ready signal is low and indicate the slave not ready to receive write commands from the master,so write command remains unchanged until local signal high and this burst write operation is complete.ortherwise,it will lead to the subsequent read signal is not be ipcore response. ----------Poor english,if wrong please advise,thank you------------ LSR
