Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

DDR3 SDRAM UNIPHY HPC problem with read

Quartusii version 13.1,CycloneV,MT41K256M16HA The main parameters uniphy hard ipcore side: memory clock 300Mhz total interface width 32: DDR3 total bit width used is 16bits capacity of 512MB...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi,everyone

I have found why the read signal is normal，but can not reproduce the DDR data .

Avalon-MM protocol: In busrt Write operation,the local_ready signal is low and indicate the slave not ready to

receive write commands from the master,so write command remains unchanged until local signal high and this

burst write operation is complete.ortherwise,it will lead to the subsequent read signal is not be ipcore response.

----------Poor english,if wrong please advise,thank you------------

LSR