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TSchu3's avatar
TSchu3
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

DDR3 DDR4 ECC signals ctrl_ecc_readdataerror

Hello, I am attempting to implement the Hard memory controller with ECC enabled for an Arria 10 device. I am looking for further information on the following signals- ctrl_ecc_readdataerror- This ...
Memory
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi @TSchu3

Is there any further question in this thread?

The ctrl_ecc_user_interrupt signal is the output conduit from EMIF IP that active when there is a bit error.

This signal should be active high.

Regards,

Adzim