TSchu3
Occasional ContributorJoined 8 years ago
User Profile
Occasional Contributor
User Widgets
Contributions
Re: GMII to RMII Converter usage restrictions
Hi thanks for confirming that the IP is supported in the Arria 10. However, I am confused on the second part of the answer. Based on the KDB link. RGMII should not work at all for Arria 10 because it fails timing. So how can the IP work with the HPS but not the Triple Speed Ethernet? Thank you438Views0likes0CommentsGMII to RMII Converter usage restrictions
Hello, I am interested in using the GMII to RGMII converter core on an Arria 10 without using the HPS. In the Embedded Peripherals guide section 49 it has a note stating this IP is only supported in Cyclone V SOC devices. Yet I am able to generate it for an Arria 10. So is this IP supported in Arria 10? Secondly, the IP is specifically designed to work with the HPS and is call the HPS GMII to RGMII Converter in the IP generator. I don't see why this would need an HPS, can it be used on its own to interface the Triple Speed Ethernet IP with an external RGMII PHY? The Triple Speed Ethernet IP only supports GMII/MII in the Arria 10. Thanks!531Views0likes3CommentsOutput raw high speed signal to SMA
Hello all, I have a test design with a simple ring oscillator. I want to measure its freq. externally with an oscilloscope. I want to export this signal to an SMA connector (single or differential). I currently have an Arria 10 GX board and a Terasic HSMC daughter board with several SMA outputs. My problem is that when I try to route the output signal through the HSMC connector I get fitment errors since the pins are not compatible with GPIO only high speed differential. Is there a way around this? Does it require using a transceiver PHY? This would not be ideal as I do not want to sample the signal. I want to observe a raw signal on the scope. Is there another way to export my signal without using a transceiver? Or the High Speed Differential pins? My understanding is that GPIO pins are limited to 300Mhz. Looking for any suggestions. Thanks!336Views0likes1CommentRe: Arria 10 M20k block usage- More block with less memory bits?
Yes, it does help to an extent. I can manipulate Quartus into using different types of memory or logic on a component by component basis. This is very time consuming and not really scalable. Any changes to the design require additional requirements. It seems to be the best we are going to get at this time, since I am un-able to send the design to you for review. Thanks717Views0likes0CommentsRe: Arria 10 M20k block usage- More block with less memory bits?
I remain very unsatisfied with the proposed possibilities. The most recent ( Best Fit vs Safe Fit) cannot be confirmed or checked. I also don't even have a definition for the two options. Either way it does nothing to explain why the Quartus compilation claims that the design needs MORE memory bits on the small chip than on the larger (see my first post). If we had a situation where the smaller chip did not fit but the number of memory bits required was consistent then I could understand why it wasn't working. But that is not the case.774Views0likes0CommentsRe: Arria 10 M20k block usage- More block with less memory bits?
Additional information- I attempted to force several memory instances to MLAB via set_instance_assignment -name RAM_BLOCK_TYPE MLAB -to <ram_instance> This had no effect. However, what did work was altering fifos in the platform designer. I discovered that Quartus was constraining all fifos to use only M20k. This seemed odd to me, so I looked at them in the platform designer. They were all set to 'Auto' under the "What should the memory block type be?". To test this out I set some of them to MLAB. Then I saw a significant reduction in M20K use and MLABs were selected instead. It seems that for some reason Quartus is interpreting 'Auto' to be constraining to M20k only? Not sure how else to explain it. These fifos are all set to 'Auto' in the successful project on the larger chip and Quartus does not constrain them to M20k there. But on this smaller chip it does.2.1KViews0likes0CommentsRe: Arria 10 M20k block usage- More block with less memory bits?
Here are my findings so far- 1- I implemented a version of the design with reduced memory just to see when it would start fitting. I discovered that when I reduce memory usage in order to fit onto the smaller chip then Quartus uses MLABS. However when I try to implement the full design and fitment fails. The report then shows 0 MLAB usage. So it is tricky to say what the problem is for the failing design. For the large Arria - It shows 2415 MLABS used. For the Small Arria with reduced memory - it shows 3653 For the full design on smaller Arria- is shows 0 Interestingly it states that MLABs can be up to 1/2 of total LABs. But in neither case does it use half. And for the Small Chip design w/ reduced memory it only uses 92% of Logic and MLABs 2- ALM usage of the Full design on smaller chip, which fails fitment is 119,902 (48%) ALM usage is 185,619 on the small chip (74%) w/ reduced memory ALM usage is 172,802 on the large chip (40%) 3- I could not see any differences in port depth. I have not yet tried forcing an instance into an MLAB. It is failing by such a large degree I'm not sure which instances to try or how many. 4 I am not able to determine whether this applies or not. Since the design fails fitment it can't run timing analysis This all brings me back to my initial question. Why does the smaller chip claim to need 36,086,072 memory bits and 3,055 blocks , when the larger chip only needs 35,349,568 bits and 2713 blocks? Also please note that 36,086,072 bits is only 83% of the smaller Arria chip and should fit (in my experience). Thanks again.2.1KViews0likes1CommentRe: Arria 10 M20k block usage- More block with less memory bits?
Hi, I'm still digging through this as time permits. I will update later today or next week. I am still skeptical that any of the above listed options will explain the current problem but I will check them all. Thanks2.2KViews0likes0Comments