DDR2 with Terasic's DE-4 board

Hi:

You are probably not doing the pll reconfiguration. With high speed DDR2 timing, you need to find the appropriate PLL phase setting for the read/write to work.

This is discussed in the altmemphy documentation found at:

http://www.altera.com/literature/ug/ug_altmemphy.pdf

The altpll-recofig documentation is also required to understand the sequence.

http://www.altera.com/literature/ug/ug_altpll_reconfig.pdf

The Nios software, is probably doing this calibration at startup, so if you dig though the sample code you'll probably see it doing the PLL reconfiguration to adjust the read and write timing.

The I2C interface allows the NIOS to read the ram information, letting you know how much ram is out there, what it's RAS/CAS latency is, etc. This is not strictly required if you know the info for the module you are using, but allows for adjustments for various modules.

Regards

Pete