DDR2 Troubles on Cyclone III

agdepus - Thanks again for your help. I am running my tools on Linux, Centos 5.5. My experience with the NIOS and SOPC builder tools on Windows 7 has not been good. Right now most of our designs are all V9.1 of the tool set and so I don't know if V10 is any better. If you go to Linux, I suggest CentOS. That worked for me without issue, is free, and has a wider range of software available than Suse and RHEL.

Yes, I'm using a bridge, and have a very similar setup to what you described. However, my NIOS is running at 125MHz.

I'm trying to bring this design up on a new custom board. I've got the identical design working correctly on the Altera Cyclone III dev kit, and the design meets FPGA timing in both the DevKit and the custom PCB.

However, the four variables that are different between our PCB and the Dev Kit:

1. We are using two 256Mb DDR2 ICs MT47H16M16, the Dev Kit uses two MT47H32M16 (512 MB) - and so our PCB design is using a different memory Preset file.

2. Our PCB uses separate clocks for each of the DDR2 ICs, the Dev Kit uses one clock that Tees - once again we have two clocks set up in the preset file.

3. I'm using a EP3C55F780C7N rather than the EP3C120F780C7N on the dev kit - so the pinout on the FPGA is a slight different.

4. Of course, the layout is different.

My suspicion is that that something in the layout or the Dual clock architecture is causing the problems I'm seeing. The fact that the lower bytes are solid, but the upper bytes are corrupt or have slipped a clock seems curious as well. It seems there is enough adjustably in the DDR core that there may be a fix here, but I'm not sure what to tweak.