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Altera_Forum
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17 years ago

DDR2 reading errors on last two words

Hi, I've some problems with my ddr2 design. I use Altera DDR2 high performance IP on pci express dev board (Stratix II GX). I build some logic around my memory controler in order to test...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Sounds to me like an unaligned memory access issue.

Check the data width of your controller, the address locations you can access are only multiples of the data width.

For example, a 64-bit data width, addressing can only happen at these addresses : 0x0, 0x64, 0x128, 0x192, 0x256...etc

Cheers,

Thean Charn