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Honored Contributor
Honored ContributorDDR2 on two sides - one controller
Hello, We are using an Arria II with DDR2 chips on two sides of the FPGA. Is there a way to aggregate the two and control them with one instance of the DDR2 HP controller? We are using HP and...
Altera_ForumHonored Contributor
Honored ContributorThe wrapper I use has command and data fifos already. The wrapper also allows multiple readers/writers to access the DDR in a slice fashion. So, I think I will follow your advice and add another fifo layer to stitch the two data halves together. Each read/write command uses a big enough data burst length that should compensate for any refresh hiccups. As far as timing, I use a dcfifo to cross between the ddr domain and the interface domain and it seems to work ok for the DDR frequency I am using. Using two fifos to stitch the data means that I will have 3 clock domains to deal with, but I think that will not be a problem.
And as far as the latency due to the extra fifos, that's ok because I queue up multiple commands and once the data stream starts, the throughput is adequate. Thanks again for your insight.
