DDR2 on two sides - one controller

With two independent memory controllers you will not be able to guarantee that when one throttles the other one will as well (for example when a refresh cycle occurs). So because each controller calibrates differently they are not going to be perfectly in sync with each other and as a result the local_ready signal from each controller with not behave the same at all times between the two controllers.

The solution to this problem is to buffer write data and read/write commands in a FIFO and dispatch the buffered information to each controller independently. Likewise you would need two independent read data FIFOs to catch the data returning (when both read buffers are not empty then you have a single wide word of data glued back together). These additional FIFOs are what I was eluding to when I mentioned the latency increase.

One thing you might run into is timing issues because your bridge will be wedged between two controllers on opposite sides of the chip. Depending on the clock frequency you are targetting you might need some extra pipelining. The FIFOs I mentioned might help since the input and output will be registered by the on-chip memory they instantiate. If that's not enough in SOPC Builder you would add pipeline bridges and Qsys pipeline bridges or automatic pipelining. How you do that without using those tools will require some work on your part.