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Altera_Forum
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14 years ago

DDR2 memory with ALTMEMPHY and Micron MT47H32M16HR-25E

I am having trouble setting up ddr2 memory for a micron MT47H32M16HR-25E single memory chip with Altera ALTMEMPHY with Quartus 11.1 and QSYS I have set all the timings to the data sheet from a...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Damn database error! Written a looong answer before :/ Ok shorted version:

Available options:

1) Leave full rate (125MHz) and provide perfect timing constraints, because Nios above 100MHz can't run correctly.

2) Leave full rate, but add pipeline bridge and connect all peripherals to that bridge.

3) Use it as it is now with half rate bridge at 62.5MHz.

As I said - Nios clocked above 100MHz must have perfect timing constrains.