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Altera_Forum's avatar
Altera_Forum
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16 years ago

DDR2 HP core pins plan problem!!!!

I used stratix II ep2s60f1020c5 ,

I want assigned the ddr II sdram pins to bank 8 and assigned the ddr II different clkp , clkn to bank 12 .Bank 12 is a pll bank .

I must assigned VCCIO8 , VCC_pll_out to 1.8V and the VREFB8N0，VREFB8N1 VREFB8N2 to 0.9 V.the ddr II IO standard is SSTL-18 class I.

the problem is I used bank 12 as ddr II pins。but they are belong to VREFB7N0.

if I used VREFB7N0 =0.9v ，how about the other pins in bank 7 ?

they also belong to VREFB7N0grous. I used them as standard of 3.3v-LVTLL.

Can they works well as general IO?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    I used bank 12 as ddr II pins。but they are belong to VREFB7N0

    --- Quote End ---

    No, PLL12 ("Bank12") uses adjacent bank8 VREF pins.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    oh,sorry. that is my careless, I used bank10 .

    "Banks 9 through 12 are enhanced PLL external clock output banks. These PLL banks utilize the adjacent VREF group

    when voltage-referenced standards are implemented. For example, if an SSTL input is implemented in PLL bank

    10, the voltage level at VREFB7 is the reference voltage level for the SSTL input."

    But I used bank 7 as 3.3_LVTTL.

    Is this design ok?

    thank you !!!