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Altera_Forum
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17 years ago

DDR2 HP Controller Simulation

Hi, I'm trying to simulate the DDR2 HP SDRAM controller in conjunction with a Hynix DDR2 memory model. As I'm developing in vhdl I compile the following auto generated files for the controller:...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Thanks for your hints,

@cms: I have transport-constructs for all signals, currently I'm just delaying them for 0.1 ns.

@cajun-rat: That was a good point, as I had the CAS Latency set to 5 and 3 would have been enough. But anyway the memory did send data on a read request.

Now I changed to Quartus 8.1 and updated the memory controller and it works.

Thanks,

ddtehlert