Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi Jake,
Thanks for the follow up. I do see that as the clock frequency goes down that CL follows, but in the Micron datasheets I'm looking at, they only specify DDR2 down to 400MHz. Presumably you’re correct that you could get the DDR2 CL down to 2 or 3 at a 167MHz clock rate – but in the end it sounds like the answer is that DDR2 will “at absolute best” be as fast as DDR and definitely will not be faster…given the same clock rate. The benefit as you say is lower power and ODT. But that brings up another question. The savings in board space and power consumption by using ODT would be justification for me to change, but all reference designs I’m seeing from Altera and/or Terasic are still using external termination on ALL DDR2 signals. Do you know why that is? I know this is a bit of a different topic so I can take that issue up separately. Is there any chance of the Cyclone parts (in industrial speed grade) will support higher frequencies from the HP controller in the near future? I am using 8.1 tools and will be upgrading to 10.0. Will 10.0 tools (and associated HP controller) support a higher frequency than 167MHz? Just to add a little more confusion to this – if you wiki DDR and DDR2 and DDR3 the intro section has a snippet describing performance and I don’t understand how given the same frequency that DDR2 can yield twice the transfer rate. Maybe there is a blatant error :confused: http://en.wikipedia.org/wiki/ddr_sdram (http://en.wikipedia.org/wiki/ddr_sdram) “With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 mb/s (http://en.wikipedia.org/wiki/mb/s).” http://en.wikipedia.org/wiki/ddr2_sdram (http://en.wikipedia.org/wiki/ddr2_sdram) “With data being transferred 64 bits at a time, DDR2 SDRAM gives a transfer rate of (memory clock rate) × 2 (for bus clock multiplier) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR2 SDRAM gives a maximum transfer rate of 3200 mb (http://en.wikipedia.org/wiki/megabyte)/s (http://en.wikipedia.org/wiki/second)” where does the second 2X come from!!? :eek: John