DDR SDRAM High Performance Controller - are lots of warnings normal?

Yeah this is normal unfortunately. It would be nice if Altera's IP generated no warnings but it does. They are obviously innocuous but annoying nonetheless. It's a combination of two things:

1 - Altera not producing the cleanest code. This is understandable. The IP cores are highly configurable and it's easy to see how you would not pay attention to certain cases in your code generator. Also, the warnings are typical of mistakes we all make when writing parameterizable code. (widths of registers and their assignment values for example or a signal that is used under one configuration but not another).

2 - Quartus gives an extemely large amount of information to the user. Some tools would never even report a warning like this. And indeed it's not an error. The way the code is written is perfectly legal. Quartus is choosing to inform you of the warning in the event you think it might be a coding error (like for example if I created a register but forgot to specify how wide it was). Again, not a syntax error but a coding error nonetheless.

My guideline is this: Assume the warnings from the core are harmless. Altera does of course have bugs in their IP but for the most part, don't expect the synthesis warnings to be related to any kind of bug. What you should look for are any warnings from the core that might indicate something you've done wrong in connecting it. For example, if large portions of the IP core are being synthesized away, you've probably connected something wrong. In the case of the DDR controller, this will typically result in an error because your design will have DQ pins with nothing connected to them.

Jake