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Altera_Forum
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18 years ago

DDR SDRAM controller Compilations error in Cyclone III

Hi I am trying to build a project with a Nios II/f processor and a DDR SDRAM interface on a Cyclone III FPGA. I have used the preset for the Micron MT46V14M16TG. The controller can only r...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Altera support have helped me find the last error. I had not noticed that the sdram_clk and the sdram_clk_n are both bidirectional. When this error is fixed the design compiles. I have not tested the design on my board yet, but hopefully everything works....

Altera also informed me that the error in the SDC file where numbers are written with commas instead of dots will be fixed in Quartus 7.2. Until then you will have to fix it manually yourself in the SDC file.

Regards

Tom