Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

DDR HP controller read data valid signal is not aligned with read data

i use DDR hp controller to interface a micron ddr chip mt46v32m16, two chips to form 32bit width. but when i send out read request and wait the read data and read data valid sinal, they come back ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

hi, there,

i have solved my problem, it just need a longer time reset, for example 200ms, on my board, i think this is caused by my Vref dc-dc chip don't output right when i download my new sof file for a while.

hope useful for u!