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Altera_Forum
Honored Contributor
18 years agoDDR HP controller read data valid signal is not aligned with read data
i use DDR hp controller to interface a micron ddr chip mt46v32m16, two chips to form 32bit width. but when i send out read request and wait the read data and read data valid sinal, they come back ...
Altera_Forum
Honored Contributor
18 years agoI encountered the same question as you. Hope someone can solve it !