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Altera_Forum
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14 years ago

ddr controller ip performance

Hi, I am trying high performance ddr controller in my design. But I meet some performance problem when simulating it. First, the local_init_done signal goes high very late at about 4000us, but I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

If I use quartus 10.0, the carlibration time can be minimized, but the RC delay is still very large for performance.