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Altera_Forum's avatar
Altera_Forum
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18 years ago

DDR and DDR2 Conroller: local_size

Dear, I am studying the DDR&DDR2 Controller IP. Could you please explain me the following issue: - In parameter setting phase, I set Burst Length = 4. So, when controlling the IP, I can ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Your questions seem to me related to a full rate design with 1:2 multiplexing. I would expect, that the controller core is performing dummy read respectively partial write cycles to fill the burst length. DM must be connected to allow this, however.