MinzhiWang
Occasional Contributor
1 day agoDCFIFO encounters errors during compilation
Hello Guys,
We use DC FIFO to buffer data between user logic and transceivers. We got 32 error infomations (the fifo depth is 32) during compilation:
Error(15465): WYSIWYG primitive "u_xcvr_cba|u_RxDataReg|USR_RXD_FIFO|fifo_0|dcfifo_component|auto_generated|fifo_ram|ram_block5a4" has clk0 port that must be connected
Could anyone guide us to resolve this issue?
Thanks