Data on FIFO RX of TSE MAC doesn't match with data on RGMII RX

Hi Daniel,

Thanks for replying, I am using the Intel Triple-Speed Ethernet IP for the two MAC's. So yes it's an Ethernet controller.

I have already solved the problem with the FIFO, it was something with setting the registers of the TSE MAC.

I do have another question

I am trying to upload this design on my MAX10 FPGA. Do you know if i could leave out the PHY configuration in RGMII mode so the TSE MAC would use auto negotiation to communicate to the PHY?

For now I got only one Ethernet port working, by using the "MAX 10 Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example User Guide"

Regards,

Mansur