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Altera_Forum
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7 years ago

[Cyclone V PCIe Hard IP]: Avalon to PCIe read issue

Dear all, We are using Cyclone V PCIe Hard IP core with Quartus 16.1. We are using requester/completor mode so that we can perform PCIe read and write operations from Avalon master. In our d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hello,

Thank you.

Burst doesn't seem an issue in our case. Because in our case, our master does not support burst operation and hence burst value provided by interconnect fabric to PCIe's TXS component is always 1 when we use our DMA master. If there is something else which you think we should be looking for, please let us know.

We are going to install Quartus 17.1 to see whether it helps or not.

Many thanks again,

Bhaumik