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Altera_Forum
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7 years ago

[Cyclone V PCIe Hard IP]: Avalon to PCIe read issue

Dear all, We are using Cyclone V PCIe Hard IP core with Quartus 16.1. We are using requester/completor mode so that we can perform PCIe read and write operations from Avalon master. In our d...
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Altera_Forum
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7 years ago

Hello, Bhaumik

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Apart from this, I would like to know whether it was happening during each read operation in your case or was happening sometimes. In our case, if we configure DMA to transfer 64 bytes, we are getting success in first few transfers and then we are facing such issue.

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Exactly like that. Note that, in our case, 64 bytes (512 bits) were equivalent to burscount=1, or no burst at all, because our readdata port width was exactly 512bits wide. The problem seems to be that EMIF is not accepting burst transfers when burtscount port widths don't match. I don't know why this problem happens and, for me, it seems like a very strange behavior.

Another point: this problem, for me, started when I updated from Quartus 17.0 to Quartus 18.0.

I hope this will help you

Regards