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Altera_Forum
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7 years ago

[Cyclone V PCIe Hard IP]: Avalon to PCIe read issue

Dear all, We are using Cyclone V PCIe Hard IP core with Quartus 16.1. We are using requester/completor mode so that we can perform PCIe read and write operations from Avalon master. In our d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hello,

Thank you very much for your response. I will check this and will come back to you.

Apart from this, I would like to know whether it was happening during each read operation in your case or was happening sometimes. In our case, if we configure DMA to transfer 64 bytes, we are getting success in first few transfers and then we are facing such issue.

Warm Regards,

Bhaumik