[Cyclone V PCIe Hard IP]: Avalon to PCIe read issue

Hello, Bhaumik

I've had the same problem on completing read operations (move data from the offchip memory to an internal module) for the Arria 10 device using a similar PCIe Hard IP and External Memory Interface controller. The master interface generated a read request and slave accepted it by de-asserting wait_request but not generating the readdata_valid flag. It turned out that I have a problem with my burstcount values. The following changes solved the problem:

1 - I had to make sure that master and stave burstcount ports had the same width;

2 - Burstcount values, in my case, had to be 7 bits long but the max burst value should less than or equal to 2^6 = 64. Even so, I notice that internally the external memory interface splits bursts greater than 8 into several small 8 words bursts.

Remember that bursts are counted in number of blocks, not words. I mean, if your emif readdata port is 512bits long (16 words), a burst value 8 will generate 512*8 bits answer (128 words). The readdata_valid signal will be up for 8 clock cycles, with each cycle bringing 512 consecutive bits from the external memory.

I hope this information will help you.

Regards